The von Neumann Computer Model

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The von Neumann Computer Model

  • Von Neumann computer systems contain three main building blocks:
    • the central processing unit (CPU),
    • memory,
    • and input/output devices (I/O).
  • These three components are connected together using the system bus.
  • The most prominent items within the CPU are the registers: they can be manipulated directly by a computer program.
  • The following block diagram shows major relationship between CPU components:

 

 

 

 Components of the Von Neumann Model :

  1. Memory : Storage of information (data/program)
  2. Processing Unit: Computation/Processing of Information
  3. Input: Means of getting information into the computer. e.g. keyboard, mouse
  4. Output: Means of getting information out of the computer. e.g. printer, monitor
  5. Control Unit: Makes sure that all the other parts perform their tasks correctly and at the correct time.

 

  • Communication between memory and processing unit consists of two registers:
    • Memory Address Register (MAR).
    • Memory Data Register (MDR).
  • To read,

1.      The address of the location is put in MAR.

2.      The memory is enabled for a read.

3.      The value is put in MDR by the memory.

                         To write,

0.      The address of the location is put in MAR.

1.      The data is put in MDR.

2.      The Write Enable signal is asserted.

3.      The value in MDR is written to the location specified.

 

 CPU data-path :

  • Hardware units like ALU‘s, registers, memory, etc., are linked together into a data-path.
  • The flow of bits around the data-path is controlled by the “gates” which allow the bits to flow (on) or not flow (off) through the data-path.
  • The binary instructions (1 = on; 0 = off) that control the flow are called micro-instructions.

 

  • Simplified x86 data path

 

 Memory Operations :

  • There are two key operations on memory:
    1. fetch( address ) returns value without changing the value stored at that address.
    2. store( address, value ) writes new value into the cell at the given address.
  • This type of memory is random-access, meaning that CPU can access any value of the array at any time (vs. sequential access, like on a tape).
  • Such memories are called RAM (random-access memory.)
  • Some memory is non-volatile, or read-only (ROM or read-only memory.)

 

 

Understanding the MAR and the MDR :

  • MAR stands for memory address register:
    • MAR is connected to the address bus.
    • MAR is “the only way” for the CPU to communicate with address bus.
    • Tri-state buffer between MAR and the address bus prevents MAR from continously dumping its output to the address bus.
    • MAR can hold either an instruction address or a data address.

 

 

 

Understanding the MAR and the MDR, Cont. :

  • MDR Stands for memory data register.
    • MDR is connected to the data bus.
    • Data can go in both directions: to and from memory,
      • therefore, MDR can load its data from
        • the data bus (for reading data)
        • one of the CPU registers (for storing data.)
    • A 2-1 MUX circuit selects input from one of the two.

 

 

 ALU, the Processing Unit :

  • Processing unit is hardware that implements Arithmetic and Logical Operations.
  • ALU stands for Arithmetic and Logic Unit, capable of performing

·         ADD, SUBTRACT, AND, OR, and NOT

operations.

  • The size of input quantities of ALU is often referred to as word length of the computer.
  • Many processors today have word length of 32 and 64 bit.
  • Processing unit also includes a set of registers for temporary storage of data and memory addressing.

 

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